Memory modules are in common use in computer systems in the form of double in-line memory modules (“DIMMs”). An example of a conventional DIMM-type memory module 10 is shown in FIG. 1. The memory module 10 includes a circuit board substrate 14 on which several memory devices 20, typically dynamic random access memories (“DRAMs”), are mounted. In the DIMM-type memory module 10 shown in FIGS. 1, 8 memory devices 20 are mounted on each side of the substrate 14. Terminals 24 are formed along an edge of the substrate 14, which mate with slotted connectors (not shown) typically mounted on a computer system mother-board. The terminals 24 are electrically coupled to the power and signal terminals on the memory devices 20. The terminals 24 in the DIMM-type memory module 10 shown in FIG. 1 are on each side of the substrate 14. Also mounted on the substrate 14 may be a register 26 that stores command and address signals applied to the memory module 10 through the terminals 24 responsive to a clock signal that is also applied to the memory module 10 through the terminals 24. The register 26 then applies the command and address signals to the memory devices 20. Memory modules having a register 26 operating in this manner are known as “registered DRAM modules.” However, it should be understood that memory modules often do not include the register 26, and they may include components in addition to those shown in FIG. 1.
As the speed of computer systems continues to increase, the operating speed of memory devices has increased in a corresponding manner. A portion of a computer system 30 shown in FIG. 2 includes three memory modules 10a,b,c coupled to a system controller 32 though a common data bus 34, address bus 36 and command bus 38. The system controller 32 initiates a memory operation by coupling a memory request in the form of a memory command and a memory address (generally in the form of a row address and a column address) to all of the memory modules 10 through the command bus 38 and the address bus 36, respectively. If the memory operation is a write operation, the system controller 32 will also couple write data to the memory modules 10 through the data bus 34. To prevent all of the memory modules 10 from responding to the memory request, the system controller 32 also generally applies a unique chip select or similar select signal to each of the memory modules 10. A unique select signal is thus applied to each of the memory modules 10 so that only the memory module 10 receiving the select signal responds to the memory request.
The bandwidth of data between the system controller 32 and the memory modules 10 could be increased by simultaneously accessing all of the 16 memory devices 20 (FIG. 1) in each of the modules 10. For example, if the 16 memory devices 20 included in the memory module 10 could be divided into 2 sets or “ranks” of 8 memory devices and both of the ranks could be accessed at the same time, data could be read from the ranks at a rate that is 2 times faster than the rate at which data can be read from each rank of the memory devices 20. Unfortunately, data can be accessed in conventional memory modules 10 only one rank of 6 memory devices 20 at a time. As the operating speed of memory devices continue to increase, the bandwidth of data coupled from the memory modules 10 threatens to be limited by the bandwidth of the data bus 34 coupled between the system controller 32 and the memory modules 10.
Another factor that limits the operating speed of computer systems using the system controller 32 coupled to the memory modules 10 through the buses 34-38 is the need to allow for a settling time between writing data to a memory module 10 and reading data from a memory module 10. When the system controller 32 outputs data to the memory modules, the data signals are reflected from various locations, such as the junction between the data bus 34 and terminals 24 (FIG. 1) on the substrates 14 of the modules 10. Therefore, signal induced noise is present on the data bus for a considerable period after data have been written to the memory modules 10. Signal induced noise is generated on the data bus for the same reason in a read operation when one of the memory modules 10 couples data onto the data bus 34 for transfer to the system controller 32. This noise must be allowed to settle before data are subsequently written to or read from the memory modules 10 or else the noise may be mistakenly interpreted as read or write data. The need to provide for a settling time can markedly reduce the effective memory bandwidth of computer systems and other devices using memory modules.
There is therefore a need for a computer system architecture and memory module that permits a higher bandwidth of data transfer to and from memory modules and that does not require settling times between a memory accesses.